Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality.

We are looking for a  Director of Physical Design to join the SCIPS Semi-custom and Central IP Silicon team and lead a team of RTL to GDS, RTL to PD, and implementation engineers. This team delivers a variety of IP to Azure, Xbox and Surface silicon products as well test chips in cutting edge technologies. The candidate should be a motivated self-starter with the ability to lead others who will thrive in this cutting-edge technical environment.

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

Responsibilities

• Principal Physical Design, responsible for:

• Providing technical direction and managing deliverables of a team of Physical Design (PD) and implementation engineers.

• Overseeing a diverse set of projects, including soft IP (intellectual property), test chips, and mixed-signal IP development.

• Responsibilities :

• Soft IP Projects : Ensure IPs meet timing, power, and area targets.

• Test Chips : Manage all aspects of physical design, including:

• Floorplanning, bump and Electrostatic Discharge (ESD) planning.

• Synthesis, place-and-route, clock tree synthesis (CTS).

• Signoff for timing, electromigration, voltage drop, and physical verification.

• Mixed-Signal IP : Integrate complex analog IPs within a digital system, acting as a key interface between IP and System on Chip (SoC).

• Signoff Responsibility : Review signoff quality metrics prior to IP shipment and SoC tapeout.

• Collaboration : Work closely with packaging engineers on IP requirements for 2D, 2.5D, and 3D packaging options.

• Communication : Strong skills needed to coordinate with Register Transfer Level (RTL), Design for Testability (DFT), Computer-Aided Design (CAD), and SoC teams.

• Leadership :

• Provide technical direction to less-experienced physical design engineers.

• Work with limited direction and attention to detail.

• Provide clear status updates on progress, issues, and risks to management.

Qualifications

Required/Minimum Qualifications

• 9+ years of related technical engineering experience

• OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience or internship experience

• OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience

• OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience.

• 8 + years of experience in hardware design

• 3+ years of experience managing a design team

Other Requirements

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Additional or Preferred Qualifications

• 15+ years technical engineering experience

• OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience

• OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience

• OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience.

• 8+ years of experience in RTL-to-GDS tasks such as floorplanning, bump planning, synthesis, timing closure, place-and-route, electromigration & voltage drop, and physical verification

Silicon Engineering M5 - The typical base pay range for this role across the U.S. is USD $137,600 - $267,000 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $180,400 - $294,000 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

Microsoft will accept applications for the role until November 19, 2024

#AHSI #SCHIE

Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .