Sr. Design Verification Engineer

Lightmatter builds chips that enable extreme-scale artificial intelligence computing clusters. If you're a collaborative engineer or scientist who has a passion for innovation, solving challenging technical problems and doing impactful work like building the world's first optical computers, consider joining the team at Lightmatter!

As a Design Verification Engineer at Lightmatter, you will find yourself at the heart of a dynamic, interdisciplinary team. Your role will primarily involve close collaboration with our digital design experts, where you will utilize UVM testbench techniques to rigorously verify their designs. Your responsibilities will include working alongside photonic and analog designers, gaining a deep understanding of their innovative designs, and applying Real Number Modeling (RNM) and AMS verification methods. This critical function ensures the integrity of their work.

Your interaction with the Architecture team will be crucial in comprehending system requirements and spearheading performance verification. This role offers a unique platform to enhance your skills across a spectrum of areas including UVM, AMS modeling, mixed-signal verification, formal verification, emulation, and both performance modeling and verification.

Responsibilities

• Engage collaboratively with teams specializing in digital, mixed-signal, and photonics design to develop comprehensive test plans.

• Design and implement UVM testbenches for both subsystem-level and full-chip verification. This includes debugging testbenches, resolving issues, achieving high coverage, and complete the final sign-off on Design Verification (DV) with minimal guidance.

• Support development of Real Number Models (RNM) for photonics and analog circuits, conduct AMS verification in conjunction with UVM, and ensure precise model representation. Play a role in the execution of emulation and formal verification for DV purposes.

Requirements

• Bachelor’s degree or higher in Electrical or Computer Engineering or a related field

• Minimum of 5 years of design/mixed-signal verification and SystemVerilog experience

• Proficiency in a scripting language, with a preference for Python

• Expertise in developing the UVM library

• Experience with simulators such as Xcelium, ModelSim, Questa, or VCS

Preferred Qualifications

• Master’s degree or higher in Electrical Engineering, Computer Engineering, or related field with 3 years of design verification and SystemVerilog experience

• Experience with AMS verification

• Experience with formal verification

Benefits

• Comprehensive Health Care Plan (Medical, Dental & Vision)

• 401k matching

• Life Insurance (Basic, Voluntary & AD&D)

• Generous Time Off (Vacation, Sick & Public Holidays)

• Paid Family Leave

• Short Term & Long Term Disability

• Training & Development

• Flexible, hybrid workplace model

• Stock Option Plan

We offer competitive compensation. The base salary range for this role, inclusive of all US locations, is $138,000-$170,000. Your base salary will be determined based on location, experience, educational background, and market data.

Lightmatter recruits, employs, trains, compensates and promotes regardless of race, religion, color, national origin, sex, disability, age, veteran status, and other protected status as required by applicable law.