Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

• 8 years of experience with RTL design using Verilog/System Verilog and microarchitecture.

• 4 years of experience in people management, leading IP/SoC design team for low power SoCs.

• Experience with ARM-based SoCs, interconnects, and ASIC methodology.

Preferred qualifications:

• Master’s degree in Electrical/Computer Engineering, or a related field.

• 15 years of experience with IP design for clocking, interconnects, and peripherals.

• Experience with methodologies for low power estimation, timing closure, and synthesis.

• Experience managing technical teams.

• Ability to drive multi-generational roadmap for IP/SoC development.

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Silicon Design Lead, you will be part of the team that designs chassis IPs (NoC, Clock, Debug, QoS, etc.) and subsystems for Pixel SoCs. You will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver high quality RTL design. You'll solve technical problems with innovative micro-architecture, low power design methodology, and evaluate design options with complexity, performance, power, and area in mind.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $177,000-$266,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google (https://careers.google.com/benefits/) .

• Lead a team that delivers fabric interconnect IP, sub-system.

• Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.

• Oversee RTL development, debug functional/performance simulations.

• Meet schedule commitments and provide strong support to customers.

• Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCPEEOPost.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.