Microsoft Quantum has assembled a talented and diverse international team to create the world’s first scalable quantum computing system. Our full-stack approach involves exciting innovations from physics on the quantum plane to providing global quantum services. The Microsoft Quantum program strives to fundamentally change the world of computing to help solve humankind’s currently unsolvable problems. We are on the cusp of an accelerated effort in quantum computing.

This position offers an opportunity to have a meaningful influence on a revolutionary technology. The research effort includes a diverse staff of theoretical and experimental physicists, hardware designers and software engineers around the world. Our Cryogenic Complementary Metal-Oxide Semiconductor (CryoCMOS) team, is looking for a Senior Quantum Digital Application-Specific Integrated Circuit (ASIC) Design Engineer to work as digital Application Specific Integrated Circuit (ASIC) designer to participate in the research and development of essential building blocks in the control and readout chain of our quantum hardware implementations.

This role involves deep, technical work in a small, collaborative environment. We are looking for Senior Quantum Digital Application-Specific Integrated Circuit (ASIC) Design Engineer who is as passionate about their own contribution as they are to empowering and inspiring others. The Senior Quantum Digital Application-Specific Integrated Circuit (ASIC) Design Engineer will be responsible for contributing to the technical direction of the research based on system and block design ideas and simulations, experimental results, program needs and the input from cross-functional colleagues.

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day.

Responsibilities

• Contribute to the architecture, specification, design, test, and development of CryoCMOS functions and ASICs to support the full-stack quantum hardware implementations.

• Be responsible for 

• Logic design/Register Transfer Level (RTL) entry 

• RTL to GDS implementation in Physical Design domain, from synthesis to place and route of partitions through all signoffs including timing signoff, physical verification, EMIR signoff, and Low Power Verification.

• Define and implement efficient UVM-based verification environments and use them to verify+test digital designs

• Test plan, tests and infrastructure to complete functional validation of complex design and report bug/issues

• Team player that will work closely with theanalog, architecture, and cryogenics teams to optimize tradeoffs within the design.

• Conduct cryogenic and room temperature measurements of the ASICs and perform analysis and reporting of the measurement results.

• Use lab best practices and protocols.

• Work in accordance with health and safety policies and take care that your actions do not impact on the health and safety of yourself or others.

• Ensure hazards and risks are identified and controlled for within your area of responsibility.

Qualifications

Required Qualifications:

• Bachelor's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment

• OR Master's Degree in Physics, Engineering, or related field AND 4+ years experience in industry or in a research and development environment

• OR Doctorate in Physics, Engineering, or related field AND 1+ year(s) experience in industry or in a research and development environment, could include completion of a post doctoral research position

• OR equivalent experience

• 4+ years of experience in digital logic design including microarchitecture specification development, RTL coding in Verilog/System Verilog, design verification collaboration, and CDC/Lint closure 

• 4+ years of experience in synthesis, floorplanning, timing constraints, power / performance / area (PPA) trade-offs, and post-silicon debug 

   

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: 

• Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

• Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide proof of citizenship, U.S. permanent residency, or other protected status (e.g., under 8 U.S.C. § 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Preferred Qualifications:

• 10+ years of industry experience in logic design delivering complex solutions. 

• Successful Application-Specific Integrated Circuit(ASIC) tape outs in deep sub-micron technologies. 

• Good background in debugging designs as well as simulation environment. 

• Knowledge of verification principles, testbenches, Universal Verification Methodology (UVM), and coverage. 

• Deep experience with EDA software for digital design (Cadence suite).

• Experience/exposure to low-temperature circuit design and measurements is desirable.

• Knowledge of quantum physics, behaviour of semiconductors at cryogenic temperatures is desirable.

   

Quantum Engineering IC4 - The typical base pay range for this role across the U.S. is USD $117,200 - $229,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $153,600 - $250,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

Microsoft will accept applications for the role until September 24, 2024.

Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .