At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

As a core member of the PHY Design team, your responsibilities will span across various aspects for the ASIC frontend flow, which includes RTL integration, maintain the timing constraint, Synthesis, Place and Route, Static timing analysis (STA), timing closure, power optimization, and physical verification for both of block and Chip top level

You will also be responsible for interfacing with the Physical Design team on STA, timing closure and P&R, and participating in silicon bring up with the validation team.

Job requirement:

BSEE and at least 3-5 years of prior experience required. MSEE and at-lest 1-3 years of prior experience strongly preferred.

Prior experience in timing and or RTL design of high-speed interfaces.

Prior experience of collaborating with Physical Design teams in multiple successful ASIC/IP tapeouts.

Knowledge of the IP/SoC level timing closure flow and methodology.

Strong command of synthesis, STA, design for test, and design methodologies

Ability to handle multiple projects/tasks successfully

Experience in IP/ASIC timing constraints generation and timing closure. Expertise in STA tools and flow

Hands on experience in timing constraints generation and management

Proficiency in scripting languages (TCL and Perl)

Proficiency with synthesis, logic equivalence, DFT and backend related methodology and tools

Strong background in Constraint analysis and debug, using industry standard tools.

Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, atspeed and Bist testing.

Team player with a passion to innovate and can-do attitude.

Self-starter and highly motivated.

Desired skills

Knowledge of DDR/GDDR DRAM protocol; high-speed PHYs

The annual salary range for California is $131,600 to $244,400. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Additional Jobs (https://cadence.wd1.myworkdayjobs.com/addl_jobs)

Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. 
Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.